Chenyang Lv, 吕晨阳

Master Student (2021-2024)

Biography

Education

Expertise

  • Machine Learning for electronics design automation
  • Reinforcement Learning

Publications

  1. Finetuned Decision Transformer with Tree Search for Logic Synthesis Optimization In International Symposium of EDA (ISEDA'25) (2025)
  2. HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers CCF-B In Proceedings of Design, Automation and Test in Europe Conference (DATE'25) (2025)
  3. High-Quality Iterative Logic Compiler for In-Memory SIMD Computation with Tight Coupling of Synthesis and Scheduling In 34th International Workshop on Logic & Synthesis (IWLS'25) (2025) Best Student Paper Award Nomination
  4. A Recursive Partition-Based In-Memory SIMD Computation Scheduler for Memory Footprint Minimization CCF-A IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD'24) (2024)
  5. ERL-LS: Accelerating the Optimization of Logic Synthesis with Evolutionary Reinforcement Learning In Proceedings of International Symposium of Electronic Design Automation (ISEDA) (2024)
  6. GPT-LS: Generative Pre-Trained Transformer with Off-line Reinforcement Learning for Logic Synthesis CCF-B In Proceedings of 41st IEEE International Conference on Computer Design (ICCD) (2023)
  7. VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations CCF-A IEEE Transactions on Computers (TC) (2023)
  8. XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph CCF-C In Proceedings of the 2023 on Great Lakes Symposium on VLSI (GLSVLSI'2023) (2023)
  9. Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System In 2022 23rd International Symposium on Quality Electronic Design (ISQED'22) (2022)