Publications

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Remark: * indicates student I (co-)supervised.

Remark: = indicates equal contribution.

Remark: ✉ indicates correspondence.

2025

  1. HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers Yiyao Yang*, Fu Teng*, Pengju Liu*, Mengnan Qi, Chengyang Lv, Ji Li, Xuhong Zhang, and Zhezhi He✉ In Proceedings of Design, Automation and Test in Europe Conference (DATE)

2024

  1. A Recursive Partition-Based In-Memory SIMD Computation Scheduler for Memory Footprint Minimization Xingyue Qian, Chengyang Lv, Zhezhi He✉, and Weikang Qian✉ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’24)
  2. BKDSNN: Enhancing the Performance of Learning-based Spiking Neural Networks Training with Blurred Knowledge Distillation Zekai Xu*, Kang You*, Xiang Wang, Qinghai Guo, and Zhezhi He✉ In Proceedings of The 18th European Conference on Computer Vision (ECCV) 2024
  3. Obtaining Optimal Spiking Neural Network in Sequence Learning via CRNN-SNN Conversion Jiahao Su*, Kang You*, Zekai Xu*, and Zhezhi He✉ In Proceedings of 33rd International Conference on Artificial Neural Networks (ICANN)
  4. SpikeZIP-TF: Conversion is All You Need for Transformer-based SNN Kang You*=, Zekaiu Xu*=, Chen Nie*, Zhijie Deng, Qinghai Guo, Xiang Wang, and Zhezhi He✉ In Proceedings of Forty-First International conference on Machine Learning (ICML)
  5. CLLMs: Consistency Large Language Models Siqi Kou, Lanxiang Hu, Zhezhi He, Zhijie Deng, and Hao Zhang In Proceedings of Forty-First International conference on Machine Learning (ICML)
  6. ERL-LS: Accelerating the Optimization of Logic Synthesis with Evolutionary Reinforcement Learning Chenyang Lv*, Boning Zhang*, Weikang Qian, and Zhezhi He✉ In Proceedings of International Symposium of Electronic Design Automation (ISEDA)
  7. An Efficient Logic Operation Scheduler For Minimizing Memory Footprint Of In-memory SIMD Computation Xingyue Qian, Zhezhi He✉, and Weikang Qian✉ In Proceedings of Design, Automation and Test in Europe Conference (DATE)
  8. PIMLC: Logic Compiler for Bit-serial Based PIM Chenyu Tang*, Chen Nie*, Weikang Qian, and Zhezhi He✉ In Proceedings of Design, Automation and Test in Europe Conference (DATE)

2023

  1. Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T-4R structure for high-density memory Maosong Xie=, Yueyang Ji=, Chen Nie*, Zuheng Liu, Alvin Tang, Shiquan Fan, Xiaoyao Liang, Li Jiang, Zhezhi He✉, and Rui Yang✉ Nature Communications
  2. GPT-LS: Generative Pre-Trained Transformer with Off-line Reinforcement Learning for Logic Synthesis Chenyang Lv*, Ziling Wei*, Weikang Qian, Junjie Ye, Chang Feng, and Zhezhi He✉ In Proceedings of 41st IEEE International Conference on Computer Design (ICCD)
  3. ✭Best Paper Nomination✭ GIM: Versatile GNN Acceleration with Reconfigurable Processing-in-Memory Chen Nie*, Guoyang Chen, Weifeng Zhang, and Zhezhi He✉ In Proceedings of 41st IEEE International Conference on Computer Design (ICCD)
  4. HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Li Jiang, Naifeng Jing, and Xiaoyao Liang In Proceedings of 41st IEEE International Conference on Computer Design (ICCD)
  5. VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations Chen Nie*, Chenyu Tang*, Jie Lin, Huan Hu, Chenyang Lv*, Ting Cao, Weifeng Zhang, Li Jiang, Xiaoyao Liang, Weikang Qian, Yanan Sun, and Zhezhi He✉ IEEE Transactions on Computers (TC)
  6. XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph Chen Nie*, Xianjue Cai, Chenyang Lv*, Chen Huang, Weikang Qian✉, and Zhezhi He✉ In Proceedings of the 2023 on Great Lakes Symposium on VLSI (GLSVLSI’2023)
  7. PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy Tao Yang, Hui Ma, Yilong Zhao, Fangxin Liu, Zhezhi He, Xiaoli Sun, and Li Jiang In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE’2023)
  8. Model Extraction Attacks on Split Federated Learning Jingtao Li, Adnan Siraj Rakin, Xing Chen, Li Yang, Zhezhi He, Deliang Fan, and Chaitali Chakrabarti arXiv preprint arXiv:2303.08581

2022

  1. N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores Yu Gong*=, Zhihan Xu*=, Zhezhi He✉, Weifeng Zhang, Xiaobing Tu, Xiaoyao Liang, and Li Jiang✉ In Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’22)
  2. HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine Qidong Tang*, Zhezhi He✉, Fangxin Liu, Zongwu Wang, Yiyuan Zhou, Yinghuan Zhang, and Li Jiang✉ In Proceedings of 27th Asia and South Pacific Design Automation Conference (ASP-DAC’22)
  3. ✭Best Paper Award✭ Self-Terminating Writing of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing Zongwu Wang*, Zhezhi He✉, Rui Yang, Shiquan Fan, Jie Lin, Yueyang Jia, Chenxi Yuan, Qidong Tang, and Li Jiang✉ In Proceedings of IEEE Design, Automation and Test in Europe Conference (DATE’22)
  4. ResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning Jingtao Li, Adnan Siraj Rakin, Xing Chen, Zhezhi He, Deliang Fan, and Chaitali Chakrabarti In IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR’22)
  5. DTATrans: Leveraging Dynamic Token-based Quantization with Accuracy Compensation Mechanism for Efficient Transformer Architecture Tao Yang, Hui Ma, Xiaoling Li, Fangxin Liu, Yilong Zhao, Zhezhi He, and Li Jiang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’22)
  6. SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator Fangxin Liu, Zongwu Wang, Yongbiao Chen, Zhezhi He, Tao Yang, Xiaoyao Liang, and Li Jiang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’22)
  7. Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System Chen Nie, Zongwu Wang, Qidong Tang, Chenyang Lv, Li Jiang, and Zhezhi He In 2022 23rd International Symposium on Quality Electronic Design (ISQED’22)
  8. SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Tao Yang, Zhezhi He, Xiaokang Yang, and Li Jiang In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC’22)
  9. EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and Li Jiang In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC’22)
  10. PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration Fangxin Liu, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, Zhezhi He, Rui Yang, Qidong Tang, Tao Yang, Cheng Zhuo, and Li Jiang In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC’22)
  11. DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture Tao Yang, Dongyue Li, Zhuoran Song, Yilong Zhao, Fangxin Liu, Zongwu Wang, Zhezhi He, and Li Jiang In (DATE-22) 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE’22)

2021

  1. SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network Fangxin Liu, Wenbo Zhao, Yilong Zhao, Zongwu Wang, Tao Yang, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and Li Jiang In IEEE International Conference on Computer Design (ICCD’21)
  2. Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, and Li Jiang In International Conference On Computer Aided Design (ICCAD’21)
  3. AdaptiveGCN: Efficient GCN Through Adaptively Sparsifying Graphs Dongyue Li*, Tao Yang, Lun Du, Zhezhi He✉, and Li Jiang✉ In Proceedings of the 30th ACM International Conference on Information & Knowledge Management (CIKM’21)
  4. NeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing Jingtao Li, Zhezhi He, Adnan Siraj Rakin, Deliang Fan, and Chaitali Chakrabarti In IEEE International Symposium on Hardware Oriented Security and Trust (HOST’21)
  5. Improving Neural Network Efficiency via Post-training Quantization with Adaptive Floating-Point Fangxin Liu, Wenbo Zhao, Zhezhi He, Yanzhi Wang, Zongwu Wang, Changzhi Dai, Xiaoyao Liang, and Li Jiang In International Conference on Computer Vision (ICCV’21)
  6. MetaGater: Fast Learning of Conditional Channel Gated Networks via Federated Meta-Learning Sen Lin, Li Yang, Zhezhi He, Deliang Fan, and Junshan Zhang In IEEE 18th International Conference on Mobile Ad Hoc and Smart Systems (MASS’21)
  7. Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support Chen Nie*, Jie Lin, Huan Hu, Li Jiang, Xiaoyao Liang, and Zhezhi He✉ In Proceedings of Great Lakes Symposium on VLSI 2021 (GLSVLSI’21)
  8. Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication Yilong Zhao, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and Li Jiang In Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI’21)
  9. ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator Zhuoran Song, Dongyue Li, Zhezhi He, Xiaoyao Liang, and Li Jiang In 2021 IEEE International Symposium on Circuits and Systems (ISCAS)
  10. PIMGCN: A ReRAM-based PIM Design for Graph Convolutional Network Acceleration Tao Yang, Dongyue Li, Yibo Han, Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Zhezhi He, and Li Jiang In Proceeding of Design Automation Conference (DAC’21)
  11. Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing Yanan Sun, Chang Ma, Zhi Li, Yilong Zhao, jiachen Jiang, weikang Qian, Rui Yang, Zhezhi He, and Li Jiang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  12. Elf: Accelerate High-resolution Mobile Deep Vision with Content-aware Parallel Offloading Wuyang Zhang, Zhezhi He, Luyang Liu, Zhenhua Jia, Yunxin Liu, Marco Gruteser, Dipankar Raychaudhuri, and Yanyong Zhang In 27th Annual International Conference on Mobile Computing and Networking (MobiCom’21)
  13. RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery Jingtao Li, Adnan Siraj Rakin, Zhezhi He, Deliang Fan, and Chaitali Chakrabarti In Design, Automation and Test in Europe Conference (DATE’21)
  14. KSM: Fast Multiple Task Adaption via Kernel-wise Soft Mask Learning Li Yang, Zhezhi He, Junshan Zhang, and Deliang Fan Conference on Computer Vision and Pattern Recognition (CVPR’21)
  15. T-BFA: Targeted Bit-Flip Adversarial Weight Attack Adnan Siraj Rakin, Zhezhi He, Jingtao Li, Fan Yao, Chaitali Chakrabarti, and Deliang Fan IEEE Transactions on Pattern Analysis and Machine Intelligence (TPAMI)
  16. Non-Structured DNN Weight Pruning–Is It Beneficial in Any Platform? Xiaolong Ma, Sheng Lin, Shaokai Ye, Zhezhi He, Linfeng Zhang, Geng Yuan, Sia Huat Tan, Zhengang Li, Deliang Fan, Xuehai Qian, and others IEEE Transactions on Neural Networks and Learning Systems (TNNLS)

2020

  1. Processing-In-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency Li Yang, Zhezhi He, Shaahin Angizi, and Deliang Fan In 33rd IEEE International System-on-Chip Conference (SOCC)
  2. A Progressive Sub-Network Searching Framework for Dynamic Inference Li Yang, Zhezhi He, Yu Cao, and Deliang Fan arXiv preprint arXiv:2009.05681
  3. 2D MoS2 Based Threshold Switching Memristor For Artificial Neuron Durjoy Dev, Adithi Krishnaprasad, Mashiyat Shawkat, Zhezhi He, Sonali Das, Hee-Suk Chung, Deliang Fan, Yeonwoong Jung, and Tania Roy IEEE Electron Device Letters (EDL)
  4. Defending and Harnessing the Bit-Flip based Adversarial Weight Attack Zhezhi He, Adnan Siraj Rakin, Jingtao Li, Chaitali Chakrabarti, and Deliang Fan Conference on Computer Vision and Pattern Recognition (CVPR’20)
  5. TBT: Targeted Neural Network Attack with Bit Trojan Adnan Siraj Rakin, Zhezhi He, and Deliang Fan Conference on Computer Vision and Pattern Recognition (CVPR’20)
  6. Non-uniform DNN Structured Subnets Sampling for Dynamic Inference Li Yang, Zhezhi He, and Deliang Fan 57th Design Automation Conference (DAC’20)
  7. Defending Bit-Flip Attack through DNN Weight Reconstruction Jingtao Li, Adnan Siraj Rakin, Yan Xiong, Liangliang Chang, Zhezhi He, Deliang Fan, and Chaitali Chakrabarti 57th Design Automation Conference (DAC)
  8. Harmonious Coexistence of Structured Weight Pruning and Ternarization for Deep Neural Networks Li Yang, Zhezhi He, and Deliang Fan Thirty-third AAAI Conference on Artificial Intelligence (AAAI’20)
  9. Sparse BD-Net: A Multiplication-less DNN with Sparse Binarized Depth-wise Separable Convolution Zhezhi He, Li Yang, Shaahin Angizi, Adnan Siraj Rakin, and Deliang Fan ACM Journal on Emerging Technologies in Computing Systems (JETC)
  10. Hybrid Spin-CMOS Polymorphic Logic Gate With Application in In-Memory Computing Shaahin Angizi, Zhezhi He, An Chen, and Deliang Fan IEEE Transactions on Magnetics

2019

  1. Network-based multi-task learning models for biomarker selection and cancer outcome prediction Zhibo Wang, Zhezhi He, Milan Shah, Teng Zhang, Deliang Fan, and Wei Zhang Oxford academic Bioinformatics
  2. Artificial Neuron using Ag/2D-MoS 2/Au Threshold Switching Memristor Durjoy Dev, Adithi Krishnaprasad, Zhezhi He, Sonali Das, Mashiyat Sumaiya Shawkat, Madison Manley, Olaleye Aina, Deliang Fan, Yeonwoong Jung, and Tania Roy In Device Research Conference (DRC)
  3. Bit-Flip Attack: Crushing Neural Network with Progressive Bit Search Zhezhi He=, Adnan Siraj Rakin=, and Deliang Fan In International Conference on Computer Vision (ICCV’19)
  4. Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach? Shaahin Angizi, Zhezhi He, Dayane Reis, Sharon Xiaobo Hu, Wilman Tsai, Shy Jay Lin, and Deliang Fan In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
  5. Parametric Noise Injection: Trainable Randomness to Improve Deep Neural Network Robustness against Adversarial Attack Zhezhi He=, Adnan Siraj Rakin=, and Deliang Fan Conference on Computer Vision and Pattern (CVPR)
  6. Simultaneously Optimizing Weight and Quantizer of Ternary Neural Network using Truncated Gaussian Approximation Zhezhi He, and Deliang Fan Conference on Computer Vision and Pattern Recognition (CVPR)
  7. Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping Zhezhi He, Jie Lin, Rickard Ewetz, Jiann-Shiun Yuan, and Deliang Fan 56-th Design Automation Conference (DAC)
  8. Optimize Deep Convolutional Neural Network with Ternarized Weights and High Accuracy Zhezhi He, Boqing Gong, and Deliang Fan IEEE Winter Conference on Applications of Computer Vision (WACV)
  9. Binarized Depthwise Separable Neural Network for Object Tracking in FPGA Li Yang, Zhezhi He, and Deliang Fan Great Lakes Symposium on VLSI (GLSVLSI)
  10. MRIMA: An MRAM-based In-Memory Accelerator Shaahin Angizi, Zhezhi He, Amro Awad, and Deliang Fan IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  11. ParaPIM: A Parallel Processing-In-Memory Accelerator for Binary-Weight Deep Neural Networks Shaahin Angizi, Zhezhi He, and Deliang Fan In Proceedings of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC)

2018

  1. DIMA: A Depthwise CNN In-Memory Accelerator Shaahin Angizi, Zhezhi He, and Deliang Fan In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
  2. PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks Adnan Siraj Rakin, Shaahin Angizi, Zhezhi He, and Deliang Fan In 2018 IEEE 36th International Conference on Computer Design (ICCD)
  3. A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference Li Yang, Zhezhi He, and Deliang Fan In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED)
  4. Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM Zhezhi He, Shaahin Angizi, and Deliang Fan In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
  5. ✭Best Paper Award✭ BD-NET: A Multiplication-Less DNN with Binarized Depthwise Separable Convolution Zhezhi He, Shaahin Angizi, Adnan Siraj Rakin, and Deliang Fan In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
  6. HielM: Highly Flexible In-Memory Computing using STT MRAM Farhana Parveen, Zhezhi He, Shaahin Angizi, and Deliang Fan In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
  7. IMCE: Energy-Efficient Bit-wise In-memory Convolution Engine for Deep Neural Network Shaahin Angizi, Zhezhi He, Farhana Parveen, and Deliang Fan In Proceedings of the 23rd Asia and South Pacific Design Automation Conference
  8. IMCS2: Novel Device-to-Architecture Co-Design for Low-Power In-Memory Computing Platform Using Coterminous Spin Switch Farhana Parveen, Shaahin Angizi, Zhezhi He, and Deliang Fan IEEE Transactions on Magnetics
  9. Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks Shaahin Angizi, Zhezhi He, Yu Bai, Jie Han, Mingjie Lin, Ronald F DeMara, and Deliang Fan In Proceedings of the 2018 on Great Lakes Symposium on VLSI
  10. Exploring A SOT-MRAM based In-Memory Computing for Data Processing Zhezhi He, Yang Zhang, Shaahin Angizi, Boqing Gong, and Deliang Fan IEEE Transactions on Multi-Scale Computing Systems
  11. CMP-PIM: An Energy-Efficient Comparator-based Processing-in-Memory Neural Network Accelerator Zhezhi He=, Shaahin Angizi=, Adnan Siraj Rakin, and Deliang Fan In Proceedings of the 55th Annual Design Automation Conference (DAC)
  12. PIMA-logic: A Novel Processing-in-Memory Architecture for Highly Flexible and Energy-Efficient Logic Computation Shaahin Angizi, Zhezhi He, and Deliang Fan In Proceedings of the 55th Annual Design Automation Conference (DAC)
  13. Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption Shaahin Angizi, Zhezhi He, Nader Bagherzadeh, and Deliang Fan IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ICCAD)

2017

  1. Energy Efficient Reconfigurable Threshold Logic Circuit with Spintronic Devices Zhezhi He, and Deliang Fan IEEE Transactions on Emerging Topics in Computing (TETC)
  2. Current-induced Dynamics of Multiple Skyrmions with Domain-wall Pair and Skyrmion-based Majority Gate Design Zhezhi He, Shaahin Angizi, and Deliang Fan IEEE Magnetics Letters
  3. Composite Spintronic Accuracy-configurable Adder for Low Power Digital Signal Processing Shaahin Angizi, Zhezhi He, Ronald F DeMara, and Deliang Fan In 2017 18th International Symposium on Quality Electronic Design (ISQED)
  4. A Tunable Magnetic Skyrmion Neuron Cluster for Energy Efficient Artificial Neural Network Zhezhi He, and Deliang Fan In Design, Automation & Test in Europe Conference & Exhibition (DATE)
  5. Developing All-Skyrmion Spiking Neural Network Zhezhi He, and Deliang Fan Neuromorphic Computing Symposium (NCS)
  6. Leveraging Dual-mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption Zhezhi He, Shaahin Angizi, Farhana Parveen, and Deliang Fan In Proceedings of the on Great Lakes Symposium on VLSI 2017 (GLSVLSI)
  7. Energy Efficient In-memory Computing Platform based on 4-terminal Spin Hall Effect-driven Domain Wall Motion Devices Shaahin Angizi, Zhezhi He, and Deliang Fan In Proceedings of the on Great Lakes Symposium on VLSI (GLSVLSI)
  8. Rimpa: A new Reconfigurable Dual-mode In-memory Processing Architecture with Spin Hall Effect-driven Domain Wall Motion Device Shaahin Angizi, Zhezhi He, Farhana Parveen, and Deliang Fan In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
  9. ✭Best Paper Award✭ Hybrid Polymorphic Logic Gate with 5-terminal Magnetic Domain Wall Motion Device Farhana Parveen, Zhezhi He, Shaahin Angizi, and Deliang Fan In IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
  10. In-memory Computing with Spintronic Devices Deliang Fan, Shaahin Angizi, and Zhezhi He In IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
  11. Low Power In-memory Computing based on Dual-mode SOT-MRAM Farhana Parveen, Shaahin Angizi, Zhezhi He, and Deliang Fan In 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
  12. Hybrid Polymorphic Logic Gate using 6 Terminal Magnetic Domain Wall Motion Device Farhana Parveen, Shaahin Angizi, Zhezhi He, and Deliang Fan In IEEE International Symposium on Circuits and Systems (ISCAS)
  13. Leveraging Spintronic Devices for Ultra-low Power In-memory Computing: Logic and Neural Network Deliang Fan, Zhezhi He, and Shaahin Angizi In IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
  14. High Performance and Energy-efficient In-memory Computing Architecture Based on SOT-MRAM Zhezhi He, Shaahin Angizi, Farhana Parveen, and Deliang Fan In IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
  15. Exploring STT-MRAM based In-memory Computing Paradigm with Application of Image Edge Extraction Zhezhi He, Shaahin Angizi, and Deliang Fan In 2017 IEEE International Conference on Computer Design (ICCD)

2016

  1. A Low Power Current-mode Flash ADC with Spin Hall Effect Based Multi-threshold Comparator Zhezhi He, and Deliang Fan In Proceedings of the 2016 International Symposium on Low Power Electronics and Design (ISLPED)